SENIOR FPGA DESIGN ENGINEER- LEAD

FPGA, RTL, DDR, VHDL, HAPS, SOC, MIPI, USB, PCI, UVM, ARM, XILINX, VIVADO
Full Time
Depends on Experience
Work from home available

Job Description

SENIOR LEAD FPGA DESIGN ENGINEER

We have the below full time position with our client in Santa Clara, CA - REMOTE FOR NOW

Pls send your resume with your salary expectation.

Hiring manager is looking for someone who can:

Interface with their customers

Drive the Development platform

Has Prototyping experience

Has done Implementation of SoC in FPGA platform

Some Video or display experience- A PLUS!!

Exp in Design, Verification, UVM

Responsibilities:

Develop FPGA designs and subsystems (involving ASICs), from concept to product including:

  • Completing implementation in RTL, RTL/netlist verification and evaluating Xilinx Vivado synthesis and P&R results for performance and cost
  • Balancing performance, area, power, complexity and timing
  • Working closely with firmware and verification teams during specification, development, Integration and Verification phases and deliver working FPGA platforms

Skills:

  • Experience with RTL Development using Verilog, System Verilog, VHDL
  • Experience working on FPGA Design projects, including work with SOC (ARM/RISC-V CPU based), MIPI, XAUI, USB, Flash, SDIO, PCI-E, and DDR# Interfaces.
  • Familiarity with Synopsys (HAPS, Proto-Compiler) OR Xilinx tools/IPs for FPGA Design and implementation.
  • Coding, debugging skills on both UVM and FPGA Platforms
Dice Id : 91117251
Position Id : FPGA-SN
Originally Posted : 6 months ago
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