Job title: ASIC Design Verification Engineer
Location: Phoenix, AZ
Duration:1-3 years contract
Experience level: 1 to 30 years
Job Description: Work with researchers and architects defining verification methodologies for each of the different core IP. Define and track detailed test plans for the different modules and top levels. Implement scalable test benches including checkers, reference models, coverage groups in System Verilog. Keep track of coverage metrics and bugs encountered and fixed. Implement self-testing directed and random tests. Support post silicon bringup and debug activities. Ability to communicate clearly. Knowledge of Python, Perl, shell scripting. Knowledge with assertions (SVA) or others. Knowledge of digital ASICs design flows.
Bachelor s degree in Electrical Engineering or Computer Science or equivalent experience.
Nice to have(Not mandatory): C, C++ coding, debugging experience. Experience as a digital design engineer. Experience with low power design. FPGA implementation and debug experience. Self-motivated and team player.
Knowledge of Python, or other scripting. Knowledge of digital ASICs design flows.