Senior Verification Engineer

Verification, UVM, SystemVerilog, writing monitors, drivers, writing constraints
Contract W2, 6 - 12 Months
$75 - $85
Travel not required

Job Description

We are looking for Senior Verification Engineer with experience in UVM

 

  • Senior verification Engineer with experience in UVM based verification writing monitors, drivers. writing constraints
  • Should have recent experience in UVM

 

Dice Id : 10195273
Position Id : 419
Originally Posted : 2 years ago
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