Note :- While applying please mention "SeAk01# Sr DFT Engineer" in the subject line..
Its a 6-12+ Months contract.
- Work with silicon team to document the DFT specifications and define the requirements.
- Develop DFT flows and methodologies on multi-million gate complex design in advanced process node.
- Implement power-aware top & block-level hierarchical MBIST and scan insertion flow.
- Generate and verify patterns for MBIST, scan and analog circuitry
- Work with internal and 3rd party mixed signal IP design teams for creating test specification, integration and test plan.
- Work with designers and physical design team on STA, physical, power and logical issues impacting DFT
- Verify DFT circuitry and interface with functional boot sequencer for power-on repair.
- Demonstrated expert knowledge and practical work experience in Memory test and/or Scan test.
- Strong fundamental knowledge of DFT techniques including MBIST, scan compression, ATPG, JTAG, BSD, IEEE 1500 & 1687 Standard
- Hands on experience with commercial DFT tools on various aspects of DFT flow, including MBIST, Scan, ATPG and Analog mixed signal test. Experience with Synopsys SMS and DFTC is a plus.
- Solid Understanding of design verification methodologies for validating DFT implementation in pre-silicon simulation
- Experience in debugging MBIST & ATPG patterns, including compressed ATPG patterns
- Excellent analytical and debugging skills and the ability to proactively solve issues
- Must have the ability to multi-task and think in a fast-paced environment
- Strong Communications skills and the ability to work with minimum supervision