WHO YOU'LL WORK WITH:
Our creative and talented team as Physical Design Lead in San Jose, CA. As a member of this team you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place&route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
WHAT YOU WILL DO:
WHO YOU ARE:
You are a HW engineer with 10+ years of related work experience with a broad mix of technologies including:
You should also have hands on experience with the following Tool sets
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns.
We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.
We Are Cisco.
170 West Tasman Dr. San Jose, CA, 95134