The main function of the Verification Engineer is to work with a group of engineers to own the design system level verification of Facebook's products. Working closely with researchers, architects, and designers in architecting methods of design verification for multiple state of the art systems. Using design verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs.
Responsible for Design verification:
- Implement testbench and scoreboards / checkers.
- Implement test sequences as per plan and debug failures.
- Achieve 100% functional, code, and power coverage.
- Write and augment existing testplans.
- Keep track of coverage metrics and bugs encountered and fixed.
- Own execution, interpretation, and reporting of verification work status and results.
- Support system bring up and debug activities.
- Work closely with designers, micro architects & f/w to resolve issues.
- Clearly communicate & articulate clearly progress / issues with project leads.
- 7+ years of proven experience as a DV engineer
- Hands on Experience with executable test plans and Coverage Driven
- Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
- Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Nice to have:
- Experience with UPF and Power Aware GLS flow
- Tcl and Python (or similar) scripting language
- ASIC design experience
- Power and performance modeling or DV (C, system C, system Verilog, or matlab)
- Power and performance FPGA validation
- Hifi4, DSP, TIE, CNN, DSP, fixed point, floating point, SONICS, python
- Experience with firmware verification
- Experience with board level verification