JEDEC Jobs

1 - 6 of 6 Jobs

Electro-Optics Packaging Design EngineerJob Title - Electro-Optics Packaging Design Engineer

NokiaCompany Name - Nokia

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On-site in Sunnyvale, California, USA

Full-time

Job Description The team you'll be a part of Network Infrastructure includes IP Routing, Optical Networks and Fixed Networks, as well as Alcatel Submarine Networks business, currently reported under "Group Common." This business group will respond to the ever-increasing demand for higher capacity, greater reliability, faster speeds, and lower costs. Responsibilities What you will learn and contribute to Leading Package Design and Architecture in collaboration with cross-functional teams and

Principal SoC Memory Subsystem ArchitectJob Title - Principal SoC Memory Subsystem Architect

Samsung Electronics AmericaCompany Name - Samsung Electronics America

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On-site in Austin, Texas, USA

Full-time

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

ESD Design EngineerJob Title - ESD Design Engineer

Qualcomm TechnologiesCompany Name - Qualcomm Technologies

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On-site in San Diego, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: This is a position in the ESD team working on ESD designs in state of art CMOS/FinFET technology nodes for Qualcomm's advanced mobile baseband, Auto, IOE/IOT & consumer products. Join QCT's IP team in designing and implementing efficient ESD protection schemes for Qualcomm's next generation chipsets. The team is involved in the complete product lifecycle including ESD design

RTL Design EngineerJob Title - RTL Design Engineer

Xoriant CorporationCompany Name - Xoriant Corporation

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Hybrid in San Jose, California, USA

Contract

Title: RTL Engineer Location: San Jose, CA | San Diego, CA | Austin Texas Duration: 6+ months (Possible Extension-Long Term Project) Job Description As a senior RTL design engineer, you will work as part of a memory controller IP design team.You will be tasked with driving the RTL design, performance and power optimization of various sub-blocks of the dynamic memory controller.Solid engineer foundation and RTL design experience is desired for success.Key responsibilities include: Produce quality

Semiconductor Reliability EngineerJob Title - Semiconductor Reliability Engineer

Kani SolutionsCompany Name - Kani Solutions

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On-site in San Jose, California, USA

Full-time

Location: San Jose, CA (Onsite) Hire Type: Permanent / Full Time Required Skills: 5+ years' experience in IC reliability engineering with hands-on experience in 1 or more related areas such as Product Engineering, Test Engineering, Failure Analysis Good understanding of Semiconductor, manufacturing process (Fab, Assembly and advanced packaging), IC test methodologies, device reliability, silicon/package fail mechanisms and symptoms Knowledge of JEDEC IC Qualification tests such as required

ASIC Failure Analysis EngineerJob Title - ASIC Failure Analysis Engineer

SwanktekCompany Name - Swanktek

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On-site in San Jose, California, USA

Full-time

Bachelor's in Electrical/Electronics Engineering or related required. Master's Preferred 5+ years of experience in failure analysis field (preferably semiconductor). Semiconductor technology and process knowledge (Fab, Assembly, and Advanced Packaging). Experience of FA techniques like Cross sectioning, X-ray, CSAM, TDR, FIB, SEM, and TEM is required. Fundamental knowledge of fault isolation technique , ATE, Scan/ATPG debug preferred. Good understanding of transistor functions and basic electron