Tcl Jobs in Santa Clara, CA

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Senior ASIC Design Engineer

Jobot

On-site in San Jose, California, USA

Full-time

This Jobot Job is hosted by: Maria Reyes Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $140,000 - $220,000 per year A bit about us: Join our dynamic team! We are a leading innovator in HD video technology. Since 2014 we revolutionized the video surveillance market with the introduction of HD-TVI (High Definition Transport Video Interface). Our groundbreaking technology has earned widespread acclaim, becoming the preferred choice for tier

ASIC Design Engineer

Jobot

On-site in San Jose, California, USA

Full-time

This Jobot Job is hosted by: Maria Reyes Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $120,000 - $150,000 per year A bit about us: Join our dynamic team! We are a leading innovator in HD video technology. Since 2014 we revolutionized the video surveillance market with the introduction of HD-TVI (High Definition Transport Video Interface). Our groundbreaking technology has earned widespread acclaim, becoming the preferred choice for tier

ASIC/RTL Design Engineer job opportunity at Santa Clara, CA / Longmont, Colorado (Onsite/Hybrid)

Infobahn Softworld Inc.

On-site in Santa Clara, California, USA

Contract

Role Title: ASIC/RTL Design Engineer - Senior Location: Santa Clara, CA / Longmont, Colorado (Onsite/Hybrid) Duration: 12+ months contract DESCRIPTION: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ens

RTL Design Engineer - Hybrid

VIVA USA INC

Hybrid in San Jose, California, USA

Contract

Title: RTL Design Engineer Description: KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project s schedule. Help to improve/automate design process. Support post-silicon product bring-up/debug. PREFERRED EXPERIENCE: Knowledge of PCIe Gen5 and PIPE specificatio

Senior Physical Design Engineer

SambaNova Systems

On-site in Palo Alto, California, USA

Full-time

Working at SambaNova This role presents a unique opportunity to shape the future of AI and the value it can unlock across every aspect of an organization's business and operations. SambaNova is hiring a Senior Physical Design Engineer who will be responsible for developing and maintaining synthesis and physical composition flow utilizing leading industry tools. In this role, you will play a unique and critical role in the development of the SambaNova DataScale system and you will be provided wi

Sr. DFT Verification Engineer, Dojo

Tesla Motors

On-site in Palo Alto, California, USA

Full-time

What to Expect Tesla's Silicon Development Group is looking for a Design-for-Test (DFT) Design Verification Engineer to work on semi-custom ASICs. You will drive state of the art in the area of testability and contribute to product coverage and quality by verifying the DFT features pre-silicon and by delivering test content for post-silicon. What You?ll Do Create Verilog/System Verilog test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST,

Design for Test Design Verification Engineer, Dojo

Tesla Motors

On-site in Palo Alto, California, USA

Full-time

What to Expect Tesla's Silicon Development Group is looking for a Design-for-Test (DFT) Design Verification Engineer to work on semi-custom ASICs. You will drive state of the art in the area of testability and contribute to product coverage and quality by verifying the DFT features pre-silicon and by delivering test content for post-silicon. What You?ll Do Create Verilog/System Verilog test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST,

Staff SOC IR Analysis Engineer, Dojo

Tesla Motors

On-site in Palo Alto, California, USA

Full-time

What to Expect We are seeking a skilled and experienced IR Analysis Engineer to join our team, specializing in System-on-Chip (SoC) and Interposer designs. As an IR Analysis Engineer, you will be responsible for analyzing and optimizing power integrity and signal integrity in complex integrated circuits. The ideal candidate will have a strong background in IR analysis methodologies, with a focus on SoC and Interposer designs. What You?ll Do Perform power integrity analysis to ensure robust powe

Camera Imaging ASIC Design Engineer

Qualcomm Technologies

On-site in Santa Clara, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > Camera Engineering General Summary: The Multimedia Camera HW team is looking for strong ASIC design engineer for an exciting opportunity to be involved in the design of world class image and video processing blocks. As a member of team, the candidate will be responsible for the following: Collaborate with hardware/system architects to micro-architect/design HW specific to Multimedia and Camera ImageSignal Proc

Staff SOC Static Timing Analysis Engineer, Dojo

Tesla Motors

On-site in Palo Alto, California, USA

Full-time

What to Expect We are seeking a highly skilled and experienced Static Timing Analysis (STA) Engineer to join our dynamic team. As an STA Engineer, you will play a critical role in the development of System-on-Chip (SoC) designs, ensuring the successful tape-out of complex integrated circuits. The ideal candidate will have a proven track record of delivering high-quality designs with excellent understanding of micro-architecture , timing methodologies and physical design concepts. What You?ll Do

Design for Testability Engineer, Autopilot AI

Tesla Motors

On-site in Palo Alto, California, USA

Full-time

What to Expect Tesla's Silicon Development Group is looking for a Design for Test Engineer to work on semi-custom ASIC design-to-production. You will drive/push state of the art in the areas of testability to enhance product coverage and quality, in order to aggressively deliver very low DPPMs, while optimizing the test cost. What You?ll Do Define and implement various DFT features Participate/contribute in silicon bring-up, characterization, and silicon test Help achieve low DPPM through high

Health Connect/Cloverleaf Integration Developer (Only W2)

3i Infotech Inc.

Remote

Contract

Job Position: Health Connect/Cloverleaf Integration Developer Job Location: Remote Duration: 9+ Months Contract Job Description Had a candidate back out for her health connect role Needs health connect cloudCloverleafTCL Replacing Cloverleaf w/ health connect cloud Very high stress and fast paced environment Looking for someone who is a self starter and can hit the ground running

Sr. Power Integrity Engineer

Lightmatter

On-site in Mountain View, California, USA

Full-time

Lightmatter is redefining what computers and human beings are capable of by delivering a fundamentally new kind of computer that calculates using light. Transistors, the workhorse of modern computers, aren't improving at the rate they once were. To scale AI, companies are building increasingly large and energy-expensive data centers-a path that is neither financially nor environmentally sustainable. By delivering ultra-high performance and energy efficiency, Lightmatter's compute engine will pow

IC Package Layout Engineer, Dojo

Tesla Motors

On-site in Palo Alto, California, USA

Full-time

What to Expect The Dojo & AutoPilot Hardware teams at Tesla are looking for an Engineer to design IC Packages. This engineer will be part of the team to define and execute the design for the next generation of AutoPilot Hardware and Dojo Super AI Computer. This is a highly visible role where you will contribute to Tesla's FSD and High Performance Computing projects. You will work closely with IC package process, SI/PI, thermal/mechanical, and PCB layout teams. This engineer will also interface w

Digital Engineer 3 - SystemVerilog

Amarx Search, Inc.

Remote

Contract

Amarx Search, Inc. amarx.com REMOTE 6+ Month W-2 Contract position Pay: $62 - $79 per hour BOE Position ID: 2567 An excellent position with a large international defense / aerospace company * Digital Engineer 3 - SystemVerilog * Please apply ONLY if you have a Bachelor's degree and 5+ years of SystemVerilog Visa sponsorship is not available for this position We can ONLY consider your application if you have: 1: 5+ years writing SystemVerilog and UVM as a primary job function 2: Experience with

Physical Design Engineer

SGS Consulting

Remote

Contract

What are the top non-negotiable skill sets required for this role? Strong understanding in the RTL2GDSII flow and design TAPEOUTS in 16nm/14nm or below process technologies.Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.Experience working with most EDA tools like DC/Genus, ICC2/INNOVUS, Primetime, Redhawk/VOLTUS, CALIBRE.Duties: develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware lo

PLM Support Engineer, 3DExperience, Engineering Technology & Operations

Tesla Motors

On-site in Palo Alto, California, USA

Full-time

What to Expect Tesla is seeking a motivated 3DEXPERIENCE PLM (Product Lifecycle Management) Support Specialist. As a part of the Engineering Technology and Operations team, your contributions will revolutionize the way our engineers develop products. You will work towards maintaining the source of truth for engineering design, ensuring the right information reaches the right people at the right time. You will play a crucial role in handling complex data across varied formats and precision, contr

STA( Static timing analysis) Lead/Engineer

R Cube Creative Consulting Inc

Remote

Third Party, Contract

Job Title: STA ( Static timing analysis) Lead/Engineer No. of positions 3 Client Name: Intel/Broadcom/Nvidia &Similar customers Location / Remote San jose , Austin - Duration: 6 months, Extendable Date of Request: 29-Feb-2024 FTE or C2C Assignment Start Date: 1 st -April ( tentative, Depends on customer) MUST HAVE KEYWORDS: Register Transfer Level (RTL) Design Verification (DV) Design for Testability (DFT) Physical Design (PD) Job Description (Please ensure Role/ Responsibilities and Skills/

Firmware Engineer

EndoSec LLC

Remote

Full-time

Firmware Engineer The Firmware Engineer will be responsible for designing, developing, testing, and maintaining embedded software that operates on microcontrollers and other hardware platforms. The primary focus will be on creating efficient, reliable, and scalable firmware solutions to enable the functionality of various electronic devices and systems. The candidate is expected to work with teams of diverse backgrounds including mathematicians, cryptographers, and physicists, as well as support

Physical Design-PTPX Power

Mirafra Inc

On-site in San Jose, California, USA

Full-time

Work closely with the Design, DV, Implementation team to define low power vectors, generate early and signoff power data using PTPX or any other low power tool.Analyze power data, and work closely with PD and design team to optimize for low power and improve overall PPA.Support in enhancing low power flows, work with tool vendors to address any power-related tool or flow issues.Hands-on skills in one of the scripting languages, Shell/TCL/Perl/PythonExperience with correlating pre-silicon power e