Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels. Develop regression strategy, methodology and tools(scripts). Define
6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing
