Verification and validation Jobs in San Jose, CA

1 - 7 of 7 Jobs

Sr. Staff Systems Verification EngineerJob Title - Sr. Staff Systems Verification Engineer

Abbott LaboratoriesCompany Name - Abbott Laboratories

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On-site in Pleasanton, California, USA

Full-time

Abbott is a global healthcare leader that helps people live more fully at all stages of life. Our portfolio of life-changing technologies spans the spectrum of healthcare, with leading businesses and products in diagnostics, medical devices, nutritionals and branded generic medicines. Our 114,000 colleagues serve people in more than 160 countries. Working at Abbott At Abbott, you can do work that matters, grow, and learn, care for yourself and family, be your true self and live a full life. Yo

Sr. SOC Verification EngineerJob Title - Sr. SOC Verification Engineer

Apple, Inc.Company Name - Apple, Inc.

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On-site in Sunnyvale, California, USA

Full-time

Summary Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and i

SOC Verification EngineerJob Title - SOC Verification Engineer

Apple, Inc.Company Name - Apple, Inc.

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On-site in Sunnyvale, California, USA

Full-time

ASIC Design Verification Engineer (Santa Clara, CA)Job Title - ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm TechnologiesCompany Name - Qualcomm Technologies

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On-site in Santa Clara, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This i

GPU Design Verification Engineer, StaffJob Title - GPU Design Verification Engineer, Staff

Qualcomm TechnologiesCompany Name - Qualcomm Technologies

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On-site in Santa Clara, California, USA

Full-time

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: Architects, designs, implements, verifies, and optimizes performance and power of GPU cores. Responsible for verification of Graphics IP , and performing pre- and post-silicon verification to verify correctness and ensure performance and power goals are met. The responsibilities of this role include: Owning and executing on key independent tasks towards program requireme

ASIC/SoC Design Verification EngineerJob Title - ASIC/SoC Design Verification Engineer

TetraMem IncCompany Name - TetraMem Inc

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On-site in Fremont, California, USA

Full-time

Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels. Develop regression strategy, methodology and tools(scripts). Define

Senior ASIC / FPGA Design Verification EngineerJob Title - Senior ASIC / FPGA Design Verification Engineer

Technical LinkCompany Name - Technical Link

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Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing