pll Jobs in california

1 - 6 of 6 Jobs

Senior Analog Design Analog EngineerJob Title - Senior Analog Design Analog Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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Agoura Hills, California, USA

Full-time

A leading chip and silicon IP company is seeking a talented Senior Analog IC Design Engineer to join its Bufferchip Design team in Agoura Hills, California. This is an exciting opportunity to work alongside some of the brightest minds in the industry on innovative products that enhance data speed and security. In this full-time role, the Senior Analog IC Design Engineer will report to the Senior Director of Engineering and play a key role in product definition and design. The position offers hig

Analog and Mixed Signal Bench Testing Engineer ContractorJob Title - Analog and Mixed Signal Bench Testing Engineer Contractor

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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Irvine, California, USA

Contract

Analog and Mixed Signal Bench Testing Engineer Contractor Overview This position involves bench testing the analog and mixed-signal portion of our IC product(s). The candidate will be responsible for executing a bench verification test plan. It involves writing multiple Python scripts to communicate with the device-under-test (DUT). The Python script also controls bench equipment such power supply, function generator, oscilloscope, temperature chamber, etc. to monitor/record the DUT response. O

Senior ASIC Clock EngineerJob Title - Senior ASIC Clock Engineer

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Remote or Santa Clara, California, USA

Full-time

NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on pe

Principal Verification EngineerJob Title - Principal Verification Engineer

Marvell Semiconductor Inc.Company Name - Marvell Semiconductor Inc.

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Irvine, California, USA

Full-time

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be

System Signal/Power Integrity EngineerJob Title - System Signal/Power Integrity Engineer

Broadcom CorporationCompany Name - Broadcom Corporation

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San Jose, California, USA

Full-time

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: System Signal/Power Integrity Engineer Responsibilities Support high data rate SerDes applications - up to 112Gbps NRZ and 224G PAM4 systemsSystem level Signal and Power Integrity design trade-offs and debugCollaborate with package, PCB, and silicon d

Clock Distribution Engineer, DojoJob Title - Clock Distribution Engineer, Dojo

Tesla MotorsCompany Name - Tesla Motors

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Palo Alto, California, USA

Full-time

The Dojo Hardware team is looking for a Clock Distribution Engineer to work in Palo Alto, CA. This Engineer will be responsible for the design and implementation of clocks at both the SOC and IP level. Responsibilities Design custom clock distribution from PLL to sub-blocks meeting low latency and jitter specs for various SOC clocks Write modular clock RTL to handle changes, integrating it into designStrong tcl knowledge to automate the clock tree generation based on bottoms-up load feedbackWor