Job Title: DFT (Design For Test) Lead
Looking for how many contractors to fill this role?: 2
Duration: 7/27/2026 to 9/30/2027 (possibly extending longer based on project timelines)
Location? US Remote Requirement: Candidate should be available to work California times, 9-5 PST**)
Rounds of interview? 1st interview is phone screen, 2nd interview is with 2-3 engineers on team
ASIC DFT experienced consulting engineers, lead-calibre. This project revision will at least go until September 2027.
Candidate Responsibilities:
* Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug
* Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
* Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
* The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Minimum Requirements: (“Must have” Qualifications)
1.Bachelor's or a Master's Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience.
2. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP’s and high speed digital/analog macros
3. Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, TempPrimetime
4. At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production
Desired Skills/Qualifications/System Experience requirements: (“Nice to have Qualifications”)
NOTE: If you require specific years of experience for the Qualifications, please outline accordingly)
1. Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production
2. Ability to quickly learn new concepts and adapt to evolving technologies
3. Excellent communication and presentation skills
4. Strong attention to detail and system level understanding of networking and photonic solutions
Additional role, initiative and group information:
Note: Provide a background of your organization and your needs for this engagement to be shared with Supplying Agencies to gain a better understanding of your organization and your needs.
You will be part of the Silicon One optics development organization as a DFT Technical Lead in Carlsbad, CA with a primary focus on Design-for-Test. You will develop and implement DFT features - ATPG, scan compression, memory BIST, memory repair to ensure high quality testable and manufacturable designs. You will contribute to the full product cycle from pre-silicon design to post-silicon debt and production qualification. You will collaborate across multiple teams throughout the silicon life cycle. Starting from implementing DFT features to lead debugging and root cause analysis of silicon failures to improve yield and reliability.
Our chips are strategically placed in Cisco’s Silicon one AI infrastructure, powering next generation network devices to support advanced AI workloads.
Never miss an opportunity! Create an alert based on the job you applied for.
