UVM Jobs in Dallas, TX

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Senior ASIC / FPGA Design Verification Engineer

Technical Link

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Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing
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Posted 60+ days ago | Updated 12 hours ago

Hardware Design Engineer

IDC Technologies

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Remote

Third Party, Contract

Dear Applicant,Hope you are doing wellWe have an urgent requirement of Hardware Design Engineer with one of our global consulting clients. Kindly click to apply if you are available and interested in the job role mentioned below.Title: Hardware Design EngineerLocation: 100% REMOTE (USA)Contract Duration -Long TermSkills Required: Years of Experience Required: 10+ overall years of experience in the field. Degrees or certifications required: BA in electrical or computer engineering degree is nice
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Posted 36 days ago | Updated 29 days ago

ASIC Verification Engineer

Q1 Technologies, Inc.

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Remote or Santa Clarita, California, USA

Full-time, Third Party, Contract

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units