Senior ASIC / FPGA Design Verification Engineer

Overview

Remote
$80 - $110
Contract - Independent
Contract - W2
Contract - 12 Month(s)
No Travel Required

Skills

VHDL
SystemVerilog
Verilog
OVM
UVM

Job Details

6 Months

Fully remote

Verification

RESPONSIBILITIES

The senior verifier will be called upon to:

  • develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;
  • apply the various techniques and approaches of the Universal Verification Methodology (UVM);
  • contribute to the development of the test infrastructure;
  • document and report problems found to designers and assist them in identifying the source of the problems;
  • support laboratory testing.

QUALIFICATIONS

  • Experience in writing test benches in SystemVerilog.
  • Knowledge of VHDL sufficient to navigate through an existing design.
  • Knowledge of UVM validation environments.
  • Knowledge of Mentor Graphics' QuestaSim digital simulator.
  • Knowledge of the Linux environment, scripting languages (Shell, Tcl, Python, "makefile").
  • Familiarity with testbed automation techniques (Jenkins)
  • Knowledge of source code management techniques (SVN, GIT).
  • Bachelor's degree in electrical engineering, computer engineering or equivalent.
  • 10 and more years of experience in digital verification.
  • Good interpersonal communication and teamwork skills.
  • Familiarity with Agile and Jira development methods.
  • Multitasking ability.