ASIC/SOC Emulation Engineer

Overview

Full Time
Part Time
Accepts corp to corp applications
Contract - Independent
Contract - W2

Skills

Test Plans
Workflow
Collaboration
Productivity
PCI Express
DDR SDRAM
Interfaces
Testing
SANS
D3.js
Data Analysis
EDA
Build Tools
Bridging
Prototyping
PASS
ASIC
Scratch
IP
Intellectual Property
System On A Chip
Integrated Circuit
Management
RTL
Debugging
Tcl
Scripting
Software Development
Emulation
Python
SystemVerilog
UVM
C
C++

Job Details

Role: ASIC/SOC Emulation Engineer

Work location: Santa Clara, CA.





Job Description:



"ASIC Emulation Engineer

Develop emulation testbenches in System Verilog and/or C/C++.

Deliver emulation and prototyping models from RTL on industry standard emulation and prototyping platforms.

Build and execute emulation test plan to ensure quality of the models and assist pre-silicon validation.

Drive emulation methodologies for HW verification and SW development.

Develop emulation tools, workflows, and infrastructure in collaboration with RTL, verification, validation, and SW teams for productivity during debug, runtime, and data analysis of results from emulation runs.

Bring up and debug PCIe, DDR and generic SOC interfaces.

Develop emulation validation components for validation efficiency in testing, debug, and automation.

Develop and drive improvements using the latest emulation technology from industry.

Partner with vendors to debug issues and deploy new emulation capabilities.



Minimum Qualifications

5+ Years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments.

Bachelor's degree in computer science, Computer Engineering, relevant technical field, or equivalent practical experience.

Experience with current emulation technologies and methods, example simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, hybrid methods.

Experience in using either ZeBU/Happs, 4/Veloce Virtual Lab, Veloce power or Palladium App emulation tools."



Key Responsibilities:

" Track record of 'first-pass success' in ASIC where emulation is one of the key validation tools.

Understanding of compilation and build flow with experience building images from scratch with necessary design modifications to adapt to emulation.

Experience with verification, SoCs or similar designs.

Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of trade-offs between performance and ease of debug.

Experience managing multiple design releases and working with cross functional teams to support and debug customer issues.

Experience with SystemVerilog and C++ to model RTL components and transactors.

Experience with post-silicon bring up, debug and reproducing issues on emulator.

Experience with Palladium & Protium tools.

Experience with Python and TCL scripting languages.

Experience interfacing with the design, verification, validation, and software development teams and understand their needs from an emulation perspective."



Mandatory skills:



"Palladium & Protium (Proficiency: 5)

Zebu/Happs (Proficiency: 5)

Python (Proficiency: 3)

SystemVerilog/UVM (Proficiency: 3)

C/C++ (Proficiency: 3)"



Optional skills:



C/C++ (Proficiency: 3)

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