System IP Design Verification Engineer (GLS verification)

Overview

On Site
$120,000 - $150,000
Full Time

Skills

Semiconductor
Design verification
Coding
Testbench
Stimulus
checkers development
coverage closure
System Verilog
UVM
CHI
AXI
ACElite
APB
Perl
Python
GLS
power vector generation
LPDDR Memory

Job Details

Role: System IP Design Verification Engineer

Location: Austin, TX, San Jose, CA (Onsite)

Full time hire or W2 Contract

Note from manager: 5 yrs experience with GLS verification.

Minimum requirements:

PhD/MS/BS in Electrical or Computer Engineering

12+ years industry experience in a design verification role

Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure.

Experience with System Verilog, UVM or equivalent

Knowledge of ARM protocols or equivalent protocols CHI, AXI, ACElite, APB

Experience with Git version control, Unix/Perl/Python scripting

Good written and verbal communication skills

Experience with GLS, power vector generation

Formal verification skills will be a plus

Combined experience with coherent interconnect, caches and LPDDR memory controllers will be a plus

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About Wise Equation Solutions Inc.