Senior VLSI CAD Engineer, Timing Methodology

Overview

On Site
USD 168,000.00 per year
Full Time

Skills

Physical Data Model
Educate
Collaboration
Computer Hardware
Database
Software Engineering
Data Analysis
EDA
Electrical Engineering
VLSI
Timing Closure
Python
Perl
Tcl
Communication
Graph Databases
Algorithms
International Relations
Information Retrieval
Investor Relations
Optimization
Place And Route
ICC
Fluency
C++
GPU
Artificial Intelligence
Recruiting
Promotions
SAP BASIS
Law

Job Details

NVIDIA's continued advancement of world-leading hardware requires a combination of the best of both external and internal EDA tools. Our team develops and deploys these highly optimized internal tools which are used across all NVIDIA product lines many thousands of times per day.

We are seeking a Senior CAD Engineer excited to innovate in strategies for complex timing, power, and IR drop closure. The role will particularly emphasize the use of Python and graph databases, but it mostly requires a strong VLSI background in static timing, physical design, and related optimization techniques. Collaborating with design teams to educate new users and get feedback from advanced users is also an important aspect. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, this is it!

What you'll be doing:
  • Develop robust flows in Python linking PrimeTime, InnovICC2, SeaHawk, and other EDA tools with internal optimization tools for timing, power, and IR drop
  • Work with designers to craft strategies for unusual timing problems that arise in multivoltage paths, pad rings, replicated hierarchy, latch loops, clock domain crossing, etc.
  • Deploy graph-based databases suitable for LLMs and other AI-based flow tools
  • Help navigate the transition from Perl/TCL/Make based flows to Python.
  • Guide new designers to efficiently use tools and help lead future tool development.
  • As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:
  • BS or MS in Electrical Engineering (or equivalent experience)
  • 6+ years experience in VLSI timing closure with some mix of both CAD and design experience.
  • Advanced experience in timing closure, including significant experience with PrimeTime
  • Fluency in Python
  • Familiarity with Perl, TCL, and Make
  • Experience in using AI-coding assistants such as Cursor
  • Strong communication and interpersonal skills

Ways to stand out from the crowd:
  • Experience with graph databases, especially in use as knowledge graphs for LLMs or GNNs.
  • Familiarity with algorithms used for timing, power, and IR drop optimization
  • Experience with place & route tools, such as Innovus or ICC2
  • Fluency in C++

NVIDIA is widely considered to be one of the technology world's most desirable employers, and due to outstanding success, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you!

The base salary range is 168,000 USD - 310,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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