ASIC Verification Engineer

You Are:

An experienced Formal Verification Engineer able to provide formal verification services for multiple blocks and IP s.

The Work:

• Developing formal verification test plan
• Drive automation of formal testbenches and ensure they are a part of regressions
• Develop assertions, cover properties and connectivity checks and debug any failures in RTL regressions
• Work with cross functional teams (DV/Arch/Design/FW)
• Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage
• Work as a team to grow together.
• Mentor and coach junior team members
• A minimum of three years of experience with Formal Verification
• Bachelor s Degree or equivalent (12 years) work experience (If an, Associate Degree with 6 years of work experience)

Bonus Points If:

• Experience working with one or more formal verification tools such as Jasper gold, VC-Formal, IFV, Questa, etc.

• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC),
• Experience in interpreting design specifications and using temporal logic assertion-based languages such as SVA
• Experience in formal property verification (FPV), Sequential Logic Equivalence Checking (SEC/SEQ/SLEC), and/or academic formal methods
• Proficiency in programing/scripting languages
• In-depth knowledge of digital logic design, chip architecture and microarchitecture
• Problem solving and debug skills for complex logic and digital designs
• Team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design