Design Verification Engineer

  • San Jose, CA
  • Posted 19 days ago | Updated 2 days ago

Overview

On Site
Depends on Experience
Full Time

Skills

uvm
systemverilog

Job Details

Experience: 6 to 15+ years of experience.

Job Requirements are as below:

Architect block and full-chip verification environments using HVLs and constrained random
techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA
Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C,SV,UVM
Debug RTL and Gate simulations and work with design engineers to verify fixes.
Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
Evaluate latest verification methodologies and develop scripts etc. to automate verification
flows.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.