RTL Engineer / Design Verification Lead

Overview

On Site
$125,000 - $175,000
Full Time
No Travel Required
Able to Provide Sponsorship

Skills

System Verilog and UVM
Python / Perl
RTL design
EDA simulation and debugging
digital logic design and verification methodologies
implementation and Architecture
Digital ASIC Core/IP designs
SoC and ARM
HBM and IP/Block Verification

Job Details

We do have multiple open roles for RTL Engineer and Design Verification Lead in Sunnyvale, CA.

Please find the JD and details below, and let us know if you interested / looking for new job.

Location: Sunnyvale, CA or Mountain View, CA (on-site)
Start Date: ASAP

Role: RTL Engineer

Open Positions: 6

Role Overview
We are urgently seeking experienced RTL Engineers to join our team. The selected candidates will be responsible for developing and executing verification plans, building robust verification environments, and collaborating closely with design teams to ensure high-quality deliverables.


Responsibilities:

  • Plan: Develop comprehensive Core Verification Plans based on micro-architecture and design specifications.
  • Develop: Architect and implement reusable, scalable verification environments using System Verilog/UVM.
  • Test: Create and run constrained-random and directed tests to achieve high functional and code coverage.
  • Debug: Analyze simulation results, root-cause complex failures, and work with design teams to resolve issues.
  • Automate: Build and maintain automation scripts (Python/Perl) to enhance verification workflows and regression management.

Requirements:

  • Mandatory expertise in System Verilog and UVM.
  • Minimum 7 years of hands-on verification experience.
  • Strong understanding of digital logic design and verification methodologies.
  • Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
  • Ability to work independently and provide technical feedback to FE RTL design teams and CPU/IP micro-architects.
  • Proficiency with industry-standard EDA simulation and debug tools.
  • Strong debugging and root-cause analysis skills.
  • Scripting experience (Python, Perl).
  • Excellent written and verbal communication skills in English.

Role: Design Verification Lead/Manager

Open Positions: 3

Job Description:Ensure the functional correctness, performance, and adherence to specifications for complex digital ASIC Core/IP designs. This role focuses on deep, unit, and core-level verification.

Responsibilities:

  • Develop comprehensive Core Verification Plans based on the unit s micro-architecture and design specification.
  • Develop: Architect and implement reusable, robust verification environments using System Verilog/UVM.
  • Test: Create and execute constrained-random and directed tests to achieve high functional and code coverage for the core unit.
  • Debug: Analyze simulation results, debug complex failures, and collaborate with the design team to root-cause and fix issues.
  • Automate: Develop and maintain scripts (Python/Perl) to enhance the verification flow and regression management.

Requirements:

  • System Verilog/UVM expertise is mandatory.
  • At least 7 years of hands-on expertise.
  • Strong grasp of digital logic design and verification methodologies.
  • Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Proven ability to work autonomously and demonstrate technical confidence when engaging with, and providing constructive feedback to, FE RTL design teams and CPU/IP micro-architects.
  • Proficiency with industry-standard EDA simulation and debug tools.
  • Solid abilities in debugging and root-cause analysis.
  • Experience with scripting (Python, Perl).
  • Excellent written and verbal communication skills in English are required.
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