Overview
On Site
$70 - $80
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - 6 Month(s)
Able to Provide Sponsorship
Skills
Automated Testing
Collaboration
Computer Hardware
Communication
Conflict Resolution
DDR SDRAM
Embedded Systems
Data Analysis
Firmware
JTAG
Manufacturing
Problem Solving
Instrumentation
ROOT
Reliability Engineering
Scripting
Signal Integrity
Test Methods
Python
Testing
C
Job Details
C2C Role
Please share Profiles at
Hi,
Urgent need,
Role : System Validation Engineer
Location : Santa Clara, CA onsite
We are seeking a skilled engineer to support DDR (DDR3/DDR4) bring-up, margining, and characterization activities. The ideal candidate will have hands-on experience in DDR diagnostics, margin testing, and qualification of different DIMMs, as well as strong scripting skills in C and Python.
Key Responsibilities
- Execute DDR3/DDR4 memory bring-up and system marginality validation (SMV) on new hardware platforms.
- Perform diagnostic testing, margining, and qualification of various DIMMs, ensuring robust signal integrity and system reliability under different process, voltage, and temperature (PVT) conditions.
- Develop and run test patterns and margining routines (e.g., PRBS, worst-case patterns) to identify and resolve marginalities and defects.
- Analyze margin plots, eye diagrams, and statistical data to assess system performance and identify root causes of failures.
- Collaborate with hardware, firmware, and validation teams to optimize memory subsystem performance and resolve issues.
- Automate test procedures and data analysis using C and Python scripting.
- Document test methodologies, results, and recommendations for design and manufacturing improvements.
Required Skills & Experience
- Proven expertise in DDR3/DDR4 memory bring-up, margining, and characterization.
- Hands-on experience with diagnostic tools and methodologies for qualifying different DIMMs.
- Strong scripting skills in C and Python for test automation and data analysis.
- Familiarity with signal integrity concepts, eye diagrams, and margining techniques.
- Experience with embedded instrumentation, BIST, or boundary scan (JTAG) is a plus.
- Ability to interpret and analyze statistical margining data.
- Excellent problem-solving and communication skills.
Thanks and regards
Shaik Wazeed
Sureminds Solutions
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