Memory Design Engineer (SRAM, CADENCE, SPECTRE & Circuit Optimization)

  • Ottawa, ON
  • Posted 1 day ago | Updated 1 day ago

Overview

On Site
Depends on Experience
Accepts corp to corp applications
Contract - W2
Contract - 12 Month(s)

Skills

Memory Design
SRAM
CADENCE
SPECTRE
Circuit Design
Timing Analysis
Compiler Automation
Physical Implementation
Monte Carlo Simulation
Design Verification
Advanced Technology Nodes

Job Details

Job Title: Memory Design Engineer (SRAM, CADENCE, SPECTRE & Circuit Optimization)
Location: Ottawa, ON (Onsite)
Duration/Term: Long-Term Contract


Job Summary:

We are seeking a highly skilled Memory Design Engineer with 2 - 13+ years of experience in mainstream SRAM tools to work on advanced memory architectures, circuit design, and physical implementation. The ideal candidate will have expertise in memory verification, characterization, and performance optimization, ensuring high-quality memory designs at advanced technology nodes (28nm and below).


Key Responsibilities:

  • Develop SRAM architecture, including Critical Path Modeling, Full Cut Analysis, and Monte Carlo Simulations.
  • Work on complete embedded memory design flow, covering:
  • Architecture, circuit design, physical implementation, compiler automation, characterization, timing, and model generation.
  • Conduct design verification, including Sense Amplifier Analysis, Self-Time Analysis, and Marginality Analysis.
  • Validate characterized data for accuracy and efficiency.
  • Ensure physical implementation impact aligns with optimal circuit performance.
  • Utilize tools like CADENCE and SPECTRE for circuit design.
  • Collaborate effectively with cross-functional teams to optimize memory solutions.
  • Drive design improvements for low power, high-speed memory architectures.


Qualifications & Required Experience:

  • 2 - 13+ years of experience in Memory Design with SRAM tools.
  • Bachelor s/Master s degree in Electrical & Electronics Engineering (E&E) or Electronics & Communication (E&C).
  • Strong expertise in CADENCE and SPECTRE for memory layout and simulation.
  • Hands-on experience with memory verification, characterization, and optimization techniques.
  • Strong communication and teamwork skills, collaborating across design and engineering teams.


Key Skills: Memory Design, SRAM, CADENCE, SPECTRE, Circuit Design, Timing Analysis, Compiler Automation, Physical Implementation, Monte Carlo Simulation, Design Verification, Advanced Technology Nodes


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