Overview
On Site
$60 - $80
Contract - W2
Contract - 12 Month(s)
Skills
SDC
Static Timing Analysis
Synopsys
CCD
Python
TCL
Primetime
Tempus
ASIC
RTL
Design Verification
Job Details
Position: SDC Engineer
Location: San Jose CA(5 Days a week ONSITE)
Long Term Contract
- Must have/Primary skills: Fullchip timing, SDC changes back to block level, Block/Full chip SDC development, Static Timing Analysis, Primetime/Tempus
What You'll Be Doing:
- Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
- Option to also do block level RTL design or block or top-level IP integration.
- Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
- Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
- Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
- Creating fullchip clocking diagrams and related documentation.
What We Are Looking For:
- Bachelor s Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master s Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience.
- Experience with block/full chip SDC development in functional and test modes.
- Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
- Understanding of related digital design concepts (eg. clocking and async boundaries)
- Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming
- Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
- Experience with Spyglass CDC and glitch analysis
- Experience using Formal Verification: Synopsys Formality and Cadence LEC.
- Experience with scripting languages such as Python, Perl, or TCL
We are looking for strong hands-on experience in 3 areas
- SDC:/Design Constraints and STA: Timing Analysis (PrimeTime) : Very good knowledge in writing Timing Constraints with these tools
- Digital Circuits: Person should be very strong in Design Fundamentals so can make right changes in RTL as needed
- Bridge: He needs to act as a bridge between Design & Physical Design team and provide solutions to meet timings through constraints
- PD Tools: Nice to have but not must have floor-planning and P&R flow work
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