Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design

Microsoft Quantum has assembled a talented and diverse international team to create the world's first scalable quantum computing system.Our full-stack approach involves excitinginnovationsfromphysicsonthe quantum plane toprovidingglobal quantum services.The Microsoft Quantum program strives to fundamentally change the world of computingtohelp solve humankind's currently unsolvable problems.We are on thecuspof an accelerated effort in quantum computing.

This position offers an opportunity to have a meaningful influence ona revolutionarytechnology. The research effort includes a diversestaff of theoreticaland experimental physicists, hardware designers and software engineers around the world.We are looking for a Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design . Our Cryo-CMOS team is looking for an experiencedapplication-specific integrated circuit (ASIC) designerto participate in the research and development of essential building blocks in the control and readout chain of our quantum hardware implementations.

Microsoft's mission is to empower every person and every organization on the planet to achieve more. At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology.

Responsibilities:

This role involves deep, technical workina small,collaborativeenvironment. We are looking for someone who isas passionate about their own contribution as they areto empoweringand inspiring others.The candidate will be responsible for contributing to thetechnicaldirection of the researchbased on system and block design ideas and simulations, experimental results,program needs and the input fromcross-functionalcolleagues.

Key Responsibilities include:

• Contribute to the architecture, specification, design, test , and development of CryoCMOS functions and ASICs to support the full-stack quantum hardware implementations.
• Be responsible for
  • Logic design/Register Transfer Level (RTL)entry
  • RTL to GDS implementation in Physical Design domain , from synthesis to place and route of partitions through all signoff s including timing signoff, physical verification, EMIR signoff, and Low Power Verification.
  • Define and implement efficient UVM-based verification environments and use them to verify+test digital designs
  • Test plan, tests and infrastructure to complete formal validation of complex design and report bug/issues
  • Effective team collaborator that will work closely with the analog, architecture, and cryogenics teams to optimize tradeoffs within the design.

• Conduct cryogenic and room temperature measurements of the ASICs and perform analysis and reporting of the measurement results.

• Uselab best practices and protocols.

• Workin accordancewithhealth and safetypolicies andtakecare that your actions do not impact on the health and safety of yourself or others.

• Ensure hazards and risks are identified and controlled for within your area of responsibility.

Other:

• Embody our Culture and Values

Qualifications:

R equired/minimum qualifications:

• Doctorate in Electrical Engineering , Computer Engineering, Computer Science, or related field AND 1+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree in Electrical Engineering , Computer Engineering, Computer Science, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Electrical Engineering , Computer Engineering, Computer Science, or related field AND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience.
• Experienceindigitallogic design including microarchitecture specification development, RTL coding in Verilog/System Verilog,designverification collaboration, CDC/Lintclosure synthesis, floorplanning, place and route timing constraint, and post-silicon debug.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

• Doctorate in Electrical Engineering , Computer Engineering, Computer Science, or related field AND 3+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree in Electrical Engineering , Computer Engineering, Computer Science, or related field AND 6+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Electrical Engineering , Computer Engineering, Computer Science, or related field AND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience.

The successful candidatewill have the following qualifications:

• 7+ years of related technical engineering experience
• 4+ years of experience indigitallogic design including microarchitecture specification development, RTL coding in Verilog/System Verilog,designverification collaboration, CDC/Lintclosure synthesis, floorplanning, place and route, timing constraint, and post-silicon debug

Desired Skills:

• 10+years of industry experience in logic design delivering complex solutions.
• SuccessfulApplication-Specific Integrated Circuit( ASIC) tape outs in deep sub-micron technologies.
• Good background in debugging designs as well as simulation environment .
• Knowledge of verification principles, testbenches, Universal Verification Methodology (UVM), and coverage.
• Experience with Logic design/Register Transfer Level (RTL)entry
• Experience in RTL to GDS implementation in Physical Design domain, from synthesis to place and route of partitions through all signoffs including timing signoff, physical verification, EMIR signoff, and Low Power Verification.
• Deep experience with EDA software for digital design ( Cadence suite).
• Experience/exposure to low-temperature circuit design and measurements is desirable .
• Knowledge of quantum physics, behaviour of semiconductors at cryogenic temperatures is desirable.
• Effective team collaboratorand proficient communication skills.
• Ability to be flexible and adapt to new situations in a rapidly changing research environment.
• Demonstrated experience with report writing and documentation .

Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: ;br>
Microsoft will accept applications for the role until July 25, 2025.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

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