Overview
On Site
$160,000 - $190,000
Full Time
Skills
Verilog RTL
Cadence
Analog design
Job Details
Sr. Analog Design Engineer Data Center Infrastructure
Job Duties:
- The Sr. Analog Design Engineer will provide full custom analog design of various blocks such as PLLs, oscillators, bandgap, LDO, voltage regulators and High voltage detection circuits
- They will work in a team environment with individual contributions to the design tasks
- Provide feasibility study for size/performance/schedule
- Plan and coordinate with Verification/AMS design to ensure full validation coverage
- Provide floor-planning and support integration of digital & analog circuit at top chip level
- Work in cooperation with the methodology and CAD groups
- Interface between different teams to ensure successful path to production
- Coordinate with other stakeholders in identifying needs and improvements
Qualifications:
- We are seeking someone with experience in 8+ years of analog and low power design using advanced deep micron process
- Proficient with Verilog RTL coding skills (Synchronous and Asynchronous state machines)
- Proficient with Hspice and other analog simulators
- Experience with Cadence schematic capture
- Experience with Linux
- Good communication skills, ability to take ownership
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