Digital Design Engineer

Overview

Remote
$85 - $100
Contract - W2
Contract - 12 Month(s)
No Travel Required

Skills

ASIC
Digital Design
RTL
UVM
Verilog
SystemVerilog
Scripting
System On A Chip
FPGA

Job Details

SENIOR DIGITAL DESIGN ENGINEER

100% REMOTE - Within USA

About the Role:

What are the top non-negotiable skill sets required for this role?

  • Experience in RTL coding, synthesis, and/or SoC Integration
  • Experience in digital design Architecture
  • Familiarity with Verilog, System Verilog coding

Duties:

  • Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture, design and verification
  • IPs integration
  • Understand Design for Verification concepts
  • Drive the top-level Architecture definition and develop the necessary RTL
  • Drive the chip-level integration, verification plan development and verification
  • Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
  • Support the test program development, chip validation and chip life until production maturity
  • Work with FPGA engineers to perform early prototyping
  • Support hand-off and integration of blocks into larger SOC environments
  • Assist with Algorithm analysis, verification, and improvement
  • Contribute to ASIC digital architecture, design, and verification

Education: BS / MS Electrical Engineering/Computer Science or equivalent experience

Must Have Skills:

  • 4+ years of experience as a Digital Design Engineer and/or a Chip Lead
  • Experience in RTL coding, synthesis and/or SoC Integration
  • Experience in digital design Architecture
  • Experience with UPF based simulation flow
  • System Verilog OVM/UVM experience
  • TCL and Python (or similar) scripting experience
  • Experience in SoC integration and ASIC architecture

Nice to Have Skills:

  • Experience in DFT/Testability requirement and test program definition
  • Experience using High Speed interfaces like PCIe, USB, MIPI
  • FPGA design
  • Tensilica DSP, TIE, CNN, fixed point, floating point, python.
  • Experience with Power Aware GLS flow

Interview Process

How many rounds of interviews? 2 rounds

Types of Interviews Technical and programming

Interview Duration 45 minutes

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