Overview
On Site
Accepts corp to corp applications
Contract - W2
Contract - Independent
Contract - 15 day((s))
Skills
FPGA
UVM
System Verlilog
FPGA design principles and architectures
QuestaSim
Synopsys VCS
FPGA verification
Python or Perl Scripting
VHDL
Job Details
Role: FPGA Verification Engineer
Location: Santa Clara, CA (Onsite from Day 1)
Contract
Must Have Skills:
FPGA Verification Engineer
Skill 1 8 + Years of in FPGA
Skill 2 5 +Years of Exp in UVM
Skill 2 5 +Years of Exp in System Verlilog
Skill 1 8 + Years of in FPGA
Skill 2 5 +Years of Exp in UVM
Skill 2 5 +Years of Exp in System Verlilog
Key Responsibilities:
- Develop and execute comprehensive verification plans for FPGA designs.
- Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog).
- Write and debug test cases to verify functionality, performance, and corner cases.
- Perform code coverage and functional coverage analysis.
- Identify and debug issues, working closely with design engineers to resolve them.
- Document verification results and provide clear and concise reports.
Skills Required:
- Strong understanding of FPGA design principles and architectures.
- Proficiency in SystemVerilog and UVM verification methodology.
- Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
- Knowledge of code coverage and functional coverage analysis.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of experience in FPGA verification.
- Experience with scripting languages (e.g., Python, Perl).
- Familiarity with hardware description languages (e.g., VHDL, Verilog).
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