Senior ESD & IO Applications Engineer

Job Description

We are seeking a Senior ESD & IO Applications Engineer to support customer-facing design, layout, simulation, and ESD implementation challenges across semiconductor technologies. This role serves as a technical bridge between customers, design teams, and library development, requiring strong hands-on experience in circuit design, layout review, simulation, and ESD methodology.

The ideal candidate will have both chip-level and system-level ESD expertise; however, candidates with strong chip-level ESD, design, and layout experience will be considered as a prioritized backup.

Key Responsibilities

Customer Technical Support

• Act as a technical escalation point for customer design, layout, and ESD-related inquiries
• Differentiate true silicon or library issues from customer implementation errors
• Support customer debug using simulation, layout review, and measurement correlation

Design & Simulation

• Support a wide range of IO specifications and interface standards
• Perform HSPICE (primary) and limited Verilog simulations to analyze IO behavior in customer applications
• Utilize simulations to identify root causes, validate fixes, and support customer recommendations
• Understand and validate Synopsys Liberty (.lib) models and their application requirements

Layout & Physical Review

• Review customer and internal layouts to identify placement, routing, DRC, and ESD-related issues
• Perform XLS and GDS reviews for chip-level and (when applicable) system-level ESD implementation
• Use layout tools to extract and document bus resistance data

Library User Guide Development

• Create and maintain Library User Guides
• Generate baseline bus resistance tables for new libraries
• Gather and document technology-specific implementation guidelines

ESD Reviews & Methodology

• Support chip-level ESD implementation and reviews
• Perform product-level ESD reviews (ideal candidate)
• Provide recommended ESD solutions aligned with industry standards and customer use cases

Required Qualifications (Baseline / Backup Profile)

(Chip-Level ESD + Design & Layout Focus)

• BS EE plus 8+ years of relevant experience OR MS EE plus 6+ years of relevant experience
• Strong knowledge of semiconductor materials, devices, and design flows
• Hands-on experience with circuit design and simulation (HSPICE, Spectre)
• Experience using CAD and verification tools (Cadence, Mentor, Synopsys)
• Semiconductor design and layout experience sufficient to support customer debug
• Familiarity with IO standards, ESD requirements, and recommended implementation practices

Preferred / Ideal Qualifications

(Full Scope: Chip-Level + System-Level ESD)

• 10+ years of experience in semiconductor design, applications, or systems engineering
• System-level and product-level ESD strategy and troubleshooting experience
• Ability to simulate real-world circuit behavior using HSPICE
• Experience correlating simulation, layout, and lab measurement data
• Prior experience in program management or senior technical leadership roles