Overview
On Site
USD 147,800.00 - 236,200.00 per year
Full Time
Skills
Test plans
Electrical engineering
SystemVerilog
Formal verification
Scripting language
ASIC
Ciena
IMPACT
Innovation
Reporting
ROOT
RTL
System on a chip
Verilog
Design
DFT
UVM
Debugging
FPGA
Emulation
ARM
MIPS architecture
Ethernet
Computer networking
Data
Perl
Job Details
Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual's passions, growth, wellbeing and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact.
Why Ciena:
Reporting to Sr. Manager ASIC Engineering, as a Senior ASIC Verification Engineer, you will:
The Must Haves:
#LI-PG1
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
Why Ciena:
- You will be a member of a successful team working at forefront of technological innovation focused on innovative technologies, flows and products. You will be working with, and learning from industry-recognized experts.
- Our team supports aninclusive, diverse and barrier-free work environment making for empowered and committed employees.
- We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families.
- Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.
Reporting to Sr. Manager ASIC Engineering, as a Senior ASIC Verification Engineer, you will:
- Develop test benches and tests for FPGAs and ASICs.
- Assist in root-causing RTL bugs.
- Develop verification models.
- Draft detailed test plans.
- Partaking in test plan and coverage analysis of the block and SOC-level verification.
The Must Haves:
- Bachelor / Master or PhD degree in Electrical Engineering coupled with proven experience in ASIC development with Verilog.
- Experience with ASIC design verification, synthesis, timing/power analysis and DFT.
- Minimum 5 years of work experience is required in ASIC Verification, including proficiency in UVM and System Verilog.
- Strong debug and lab experience.
- Knowledge of high-performance and low-power design techniques.
- Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.
- Experience with modern SoC design architectures, ARM/MiPs type processor cores, Ethernet, Networking, and Data Communications.
- Knowledge of assertion-based formal verification.
- Proficient with a scripting language like Perl.
#LI-PG1
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.