Memory Layout Engineer

  • Ottawa, ON
  • Posted 1 day ago | Updated 1 day ago

Overview

On Site
Depends on Experience
Accepts corp to corp applications
Contract - W2
Contract - 12 Month(s)

Skills

Memory Layout
CADENCE Virtuoso
SRAM
CAM
TCAM
Low Power Design
High-Speed Memory
DRC
LVS
Design for Manufacturability
Design for Yield
IC Design
Scripting Automation

Job Details

Job Title: Memory Layout Engineer
Location: Ottawa, ON (Onsite)
Duration/Term: Long-Term Contract


Job Summary:

We are seeking a highly skilled Memory Layout Engineer with expertise in MRAM, RRAM, SRAM, CAM, and TCAM. The ideal candidate will lead the design and development of memory layouts for high-density and specialty memory blocks, define architecture and floor planning, and implement advanced layout techniques for low-power, high-speed memory solutions.


Key Responsibilities:

  • Lead the design and development of memory layouts for complex ICs, including:
  • High-density SRAM memories
  • Specialty memory blocks such as CAM and other memory architectures
  • Define memory architecture and sub-block specifications.
  • Develop and implement low-power, high-speed, high-density memory layout techniques.
  • Collaborate with memory circuit designers and verification engineers for seamless integration.
  • Perform comprehensive physical verification using DRC, LVS, and other validation tools.
  • Drive Design for Manufacturability (DFM) and Design for Yield (DFY) initiatives.
  • Conduct analysis to mitigate power integrity and signal integrity issues.
  • Mentor junior engineers, providing technical guidance and best practices.
  • Utilize CADENCE Virtuoso tool for memory peripheral layout, sense amplifier layout, and decoder layout.
  • Develop automation for layout tasks using PERL, Shell, TCL, or Skill scripting.
  • Stay updated on the latest memory design trends and technologies.


Required Skills & Experience:

  • Proven expertise in memory layout design for MRAM, RRAM, SRAM, CAM, and TCAM.
  • Strong experience with memory compiler, tiler, and complete memory layout architecture.
  • Hands-on proficiency in CADENCE Virtuoso for layout and floor planning.
  • Deep understanding of low-power, high-speed memory layout optimization.
  • Knowledge of design verification methodologies (DRC, LVS).
  • Strong collaboration skills to work with circuit designers and verification teams.
  • Experience with DFM and DFY techniques for memory architectures.
  • Familiarity with scripting automation (PERL, Shell, TCL, Skill) for layout efficiency.


Key Skills: Memory Layout, CADENCE Virtuoso, SRAM, CAM, TCAM, Low Power Design, High-Speed Memory, DRC, LVS, Design for Manufacturability, Design for Yield, IC Design, Scripting Automation


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