ASIC Architect opportunity to work for a Hardware company focused on accelerating training and inference performance for large AI models

ASIC Architect
Full Time opportunity in Saratoga, CA

Position Overview

We are looking for a highly experienced ASIC Architect to contribute to the definition and implementation of industry leading networking products. This is a unique opportunity to help shape the future of AI Networking.

Responsibilities

Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications.

Collaborate with chip and system microarchitects to align ASIC architecture with system-level goals for throughput, latency, and power efficiency.

Guide modeling and feasibility analysis of packet flow behavior through the switch datapath to validate architectural choices, including throughput, latency, power and area efficiencies.

Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design implementation and handoff.

Guide integration of internal and external IPs (e.g. MAC, PCIe, SerDes) into the broader architecture. Drive interface requirements.

Participate in design reviews, performance modeling, test and verification strategies and architectural trade-off analysis.

Contribute to post-silicon validation for performance and correctness. Investigate and resolve complex issues related to ASIC data path, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects.

Qualifications

MSEE with 10+ years of experience, preferably in networking ASIC architecture and design.

Candidates with experience in related areas of computer and parallel processing architectures in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths are also highly desired.

A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert.

Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Capability to develop Architecture behavioral models is highly desired.

Experience working across the ASIC development lifecycle, from concept through productization.

Experience in high-speed I/O integration (e.g., PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable.

Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power).