Overview
Skills
Job Details
Role: RF Analog Layout Engineer.
Location: San Diego, Cupertino, or Austin
Interview: Video.
Duration: 6 Months.
MUST HAVE RF Layout 7-28nm FF (The JD had 40 but he will not look at that, I edited it below)
- Hybrid schedule (Tues, Wed, Thursday in office) 0 percent chance of remote
- Can work in San Diego, Cupertino, or Austin Preference is Cupertino because that is where he is
Key Qualifications
- Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (7nm, 28nm, FinFET, etc.)
- Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
- Solid understanding of RC delay, electromigration, and coupling
- Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
- Knowledge of CADENCE layout tools
- Excellent communication skills and able to work with cross-functional teams
- You would also have the following, if you're more experienced:
- Capability to lead other layout engineers for top-level integration
- Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
- Scripting skills in PERL or SKILL are a plus, but not required
Description
As a RF layout engineer, you will be responsible for Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking Co-work with designers on block level and top-level floorplanning Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling Top-level layout integration and verification, schedule management