Overview
On Site
$170,000 - $200,000 annually
Full Time
Skills
Mergers and Acquisitions
Signal Processing
Algorithms
Network Protocols
RTL
SystemVerilog
Debugging
Test Cases
Management
Hardware Development
FPGA
Verilog
VHDL
UVM
Communication
Artificial Intelligence
Messaging
Job Details
RESPONSIBILITIES:
Kforce's client, a fast-growing technology company delivering innovative communications products and services worldwide, is seeking a experienced Hardware Design/Verification Engineer (FPGA, UVM) in Marlborough, MA. In this role, the Hardware Design/Verification Engineer will work alongside a collaborative team of engineers developing the next generation of advanced communications systems.
Key Responsibilities:
* Develop high-speed signal processing algorithms and network protocols in FPGAs
* RTL design verification using SystemVerilog/UVM
* Develop UVM testbenches for verifying FPGA designs
* Write and debug test cases
* Participate in design/code reviews and manage UVM code revisions
* Own and resolve technical issues throughout the verification process
REQUIREMENTS:
* BS in Electrical Engineering, Computer Engineering, or related discipline
* 7+ years of related hardware design experience
* Experience with design and implementation of FPGA modules using Verilog or VHDL
* Knowledge of UVM verification
* Strong communication and collaborations skills
The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.
We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.
Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.
This job is not eligible for bonuses, incentives or commissions.
Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
By clicking ?Apply Today? you agree to receive calls, AI-generated calls, text messages or emails from Kforce and its affiliates, and service providers. Note that if you choose to communicate with Kforce via text messaging the frequency may vary, and message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You will always have the right to cease communicating via text by using key words such as STOP.
Kforce's client, a fast-growing technology company delivering innovative communications products and services worldwide, is seeking a experienced Hardware Design/Verification Engineer (FPGA, UVM) in Marlborough, MA. In this role, the Hardware Design/Verification Engineer will work alongside a collaborative team of engineers developing the next generation of advanced communications systems.
Key Responsibilities:
* Develop high-speed signal processing algorithms and network protocols in FPGAs
* RTL design verification using SystemVerilog/UVM
* Develop UVM testbenches for verifying FPGA designs
* Write and debug test cases
* Participate in design/code reviews and manage UVM code revisions
* Own and resolve technical issues throughout the verification process
REQUIREMENTS:
* BS in Electrical Engineering, Computer Engineering, or related discipline
* 7+ years of related hardware design experience
* Experience with design and implementation of FPGA modules using Verilog or VHDL
* Knowledge of UVM verification
* Strong communication and collaborations skills
The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.
We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.
Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.
This job is not eligible for bonuses, incentives or commissions.
Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
By clicking ?Apply Today? you agree to receive calls, AI-generated calls, text messages or emails from Kforce and its affiliates, and service providers. Note that if you choose to communicate with Kforce via text messaging the frequency may vary, and message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You will always have the right to cease communicating via text by using key words such as STOP.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.