Overview
On Site
Depends on Experience
Full Time
Skills
SV
UVM
AMBA
RTL
Job Details
Role: Design Verification Engineer
Location: Sunnyvale, CA or Austin, Texas
Role Purpose
Key Responsibilities:
- Strong understanding of SV, UVM, and debugging skills.
- Knowledge of AMBA protocols.
- Develop test plans based on functional and architectural requirements.
- Build UVM/System Verilog verification environments for IP/SoC testing.
- Create directed and random test cases, perform coverage analysis.
- Debug simulation failures with RTL designers.
- Execute regression runs, analyze results, and improve processes.
- Run power-aware simulations, low power checks, and work with UPF/CPF.
- Collaborate with DFT/PD/RTL teams for design quality assurance.
- Document test environments, plans, and results for reviews.
Mandatory Skills: VLSI HVL Verification .
Experience: 5-8 Years .
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