PSV Memory Validation & Emulation Engineer

Overview

On Site
Depends on Experience
Full Time

Skills

Memory
LPDDR
DDR
RISC-V
x86-64
IOMMU
Accelerator
Oscilloscope
Multimeter
Logic Analyzer
C/C++
Python

Job Details

PSV Memory Validation & Emulation Engineer

Experience: 5 to 8 years

Salary Range: DOE

Duration:3 Months

Location: San Jose, CA,USA

Client: Tessolve/ EnChargeAI

Job Description:

Define, develop, and execute functional validation for integrated SoCs, focusing on the Memory Subsystem, its interaction with CPU functions, and system-level features. Apply hardware/software tools to ensure validation coverage and performance goals. Perform silicon debug to identify root causes of failures and resolve memory subsystem issues. Develop tools and strategies for debugging high-speed memory interfaces.

Must Have:

      • B.E/M.E in Electronics & Communication Engineering
      • Knowledge of LPDDR Memory Architecture, Validation, and Debug
      • Advanced programming in C/C++ for OS kernel & systems development
      • Experience with hardware debug tools (Oscilloscope, Multimeter, Logic Analyzer)
      • Understanding of computer architecture, OS concepts, and memory management

Preferred Skills:

      • Understanding of RISC-V architecture
      • Experience with x86-64 and accelerator architectures
      • System performance benchmarking and tuning

Keywords: Memory, LPDDR, DDR, RISC-V, x86-64, IOMMU, Accelerator, Oscilloscope, Multimeter, Logic Analyzer, C/C++, Python

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