Design Verification Engineer

Name: Hardware Engineer Mid. Duration: 11 Months Location: Mountain View, CA (Preferred) The client is open to considering remote if a candidate is strong.

Duties: Note: This requisition is a reference to a Design Verification Engineer who comes with strong experience in SOC Verification, System Verilog, UVM, BFM/Driver/Monitor/Scoreboard component development, and AXI protocol.
What candidate will Be Doing:

At-least 8+ years of experience in System Verilog
At-least 8+ year of experience in UVM.
Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.

Proficient in SVTB/UVM
Proficient in debug and assertions coding
SOC Verification experience
Proficient in AXI protocol
Verification closure with team
Make/Perl/Python
Ensure customer satisfaction.
Reporting to customer on daily or weekly progress effectively

Education: Bachelor's Degree