Overview
On Site
$65 - $74
Accepts corp to corp applications
Contract - 6 month(s)
No Travel Required
Skills
MTS Silicon Design Verification Engineer
Job Details
Job Description:
- Rich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment.
- Experience in ASIC design/verification related field in IP, Subsystem or SOC level.
- Experience in writing System Verilog and/or System C models for simulation
- Working experience in writing UVM models, checkers, and stimulus, constructing UVM register models, and applying constrained random methodology in UVM test environment and stimulus.
- Compose test plan and validation vectors to ensure functional completeness
- Experience with design for verification (assertion-based design stXXgies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.).
- Versatile in any one of the high-level verification flows such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification.
- Excellent communication skills (both written and oral).
- Strong problem-solving skills.
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