SOC Design Verification Engineer

Hello

Greetings,

We are looking for SOC Design Verification Engineer, and the following below are more detailed description of the job. Please let me know your interest and reply to me with your updated resume.

Role: SOC Design Verification Engineer
Work location: Santa Clara, CA- onsite (Hybrid 3 days at the office).

Client name; Meta Platforms Technologies, LLC /Capgemini

Client id: CGEMJP00319164

Duration: Lon Term contract

Years of experience: 9+ years

Mandatory skills: UVM/SV and Synopsys/Cadence EDA Design/Verification tools,

Pluses: Python/TCL/Perl plus

Job Description:

Minimum Qualifications

Track record of 'first-pass success' in ASIC development cycles.

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

8 to 10 years of hands-on experience in System Verilog/UVM methodology

Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation.

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Preferred Qualifications

Experience verifying GPU/CPU designs.

Experience in development of UVM based verification environments from scratch.

Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs

Experience with revision control systems like Mercurial (Hg), Git or SVN.

Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet.

Experience working across and building relationships with cross-functional design, model and emulation teams.

Key Responsibilities:

Define and implement SoC verification plans, build verification test benches to enable sub-system/SoC level verification.

Develop functional tests based on verification test plan.

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.