Overview
On Site
Depends on Experience
Full Time
Skills
RTL
System Verilog
VHDL
Python
Job Details
Must haves:
RTL, SystemVerilog/VHDL and Python
Key Responsibilities:
- Design and implement RTL for high-speed networking applications
- Develop custom IP cores and integrate third-party IP
- Implement timing constraints and ensure timing closure
- Collaborate with hardware and software engineers in a classified environment
- Support design verification and debug efforts
- Oversee FPGA implementation and optimization
Requirements:
- Bachelor's degree in Electrical/Computer Engineering
- 7+ years experience in FPGA development
- Proficiency in SystemVerilog/VHDL
- Experience with Xilinx/Intel FPGA design tools
- Experience with high-speed interfaces (PCIe, Ethernet, DDR)
- Current TS//SCI clearance
Desired Skills:
- Experience with network security applications
- Knowledge of networking protocols and standards
- Experience with scripting languages (Python, Tcl)
- Familiarity with hardware security requirements
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