Design Verification Lead

Job Title: Design Verification Lead

Location: Sunnyvale, CA or Mountain View, CA (on-site)

Responsibilities:

Develop comprehensive Core Verification Plans based on the unit s micro-architecture and design specification.

Develop: Architect and implement reusable, robust verification environments using System Verilog/UVM.

Test: Create and execute constrained-random and directed tests to achieve high functional and code coverage for the core unit.

Debug: Analyze simulation results, debug complex failures, and collaborate with the design team to root-cause and fix issues.

Automate: Develop and maintain scripts (Python/Perl) to enhance the verification flow and regression management.

Required Experience

Must-Haves:

• 10+ years in SoC/ASIC design or verification
• Deep experience with custom memory interfaces, controllers, or comparable complex IP
• Strong background in UVM-based verification, testbench architecture, subsystem-level verification
• Strong RTL/Verilog/SystemVerilog, micro-architecture, synthesis, timing constraints, lint/CDC
• Familiarity with ARM-based ecosystems (AMBA interconnects, buses, debug infrastructure)
• Understanding of SoC interfaces (QSPI, UART, GPIOs, etc.)
• Ability to own specs, architecture, implementation, and reviews with minimal guidance
• Comfortable representing engineering decisions to senior client stakeholders

Bonus Points:

• Experience with DRAM memory controllers
• Experience with UCIe or other chiplet-integration technologies
• Prior leadership of complex IP block design/verification
• Strong spec interpretation and documentation discipline
• Demonstrated stability (low churn) with long-term program ownership