RTL design Engineer

  • San Jose, CA
  • Posted 7 hours ago | Updated 7 hours ago

Overview

On Site
Depends on Experience
Full Time

Skills

RTL
LINT
CDC
Integration

Job Details

Job Description:

  • Strong Logic Design, RTL coding (Verilog HDL) and debugging skills
  • Analyze and resolve Lint, CDC and RDC issues in the design
  • Understanding of low power design and validation techniques including UPF
  • Experience with constraint generation, timing closure analysis, formal verification, low power checks using UPF flows and ECO implementation.
  • Experience with writing assertions and doing negative checks to validate assertions
  • Experience with Silicon validation/Bring-up

Experience with the following are highly desired

  • ARM CPUs
  • Memory controllers
  • Peripherals such as I2C, SPI, UART, LVDS, QSPI and SPMI
  • Peripherals and interconnect protocols such as APB, AHB and AXI Experience with the following are a definite advantage
  • Scripting languages such as (Python perl/tcl)
  • Convert DV test cases to Python scripts to check Silicon functionality

Other Requirements

  • Self-motivated
  • Ability to work independently
  • Good verbal and written communication skillsAbility to work with remote and cross functional teams
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.