Overview
On Site
Depends on Experience
Accepts corp to corp applications
Contract - W2
Contract - Independent
Contract - 12 Month(s)
No Travel Required
Able to Provide Sponsorship
Skills
ASIC
Collaboration
Communication
Design Optimization
Digital Design
FPGA
Formal Verification
Static Timing Analysis
Timing Closure
Job Details
Job Title: Senior STA Engineer
Location: Bay Area, CA
Job Description:
We're looking for an experienced STA engineer with expertise in synthesis, formal verification, and timing closure. The ideal candidate will have advanced skills in Static Timing Analysis (STA) and be able to work independently on block-level timing closure.
Key Responsibilities:
- Perform STA and timing closure at block level
- Collaborate with designers to understand design intent and optimize timing
- Analyze and fix timing issues
- Run STA and timing analysis tools
- Work on block-level timing closure, ensuring design meets timing requirements
Requirements:
- Experience in synthesis, formal verification, and timing closure
- Advanced skills in Static Timing Analysis (STA)
- Ability to work independently on block-level timing closure
- Strong communication skills to interface with designers and other stakeholders
- Experience with STA tools and timing analysis methodologies
Nice to Have:
- Knowledge of digital design flows and ASIC/FPGA design
- Experience with design optimization and timing convergence
If you're a motivated and experienced STA engineer looking for a new challenge, let's connect!
Location: Bay Area, CA
Job Description:
We're looking for an experienced STA engineer with expertise in synthesis, formal verification, and timing closure. The ideal candidate will have advanced skills in Static Timing Analysis (STA) and be able to work independently on block-level timing closure.
Key Responsibilities:
- Perform STA and timing closure at block level
- Collaborate with designers to understand design intent and optimize timing
- Analyze and fix timing issues
- Run STA and timing analysis tools
- Work on block-level timing closure, ensuring design meets timing requirements
Requirements:
- Experience in synthesis, formal verification, and timing closure
- Advanced skills in Static Timing Analysis (STA)
- Ability to work independently on block-level timing closure
- Strong communication skills to interface with designers and other stakeholders
- Experience with STA tools and timing analysis methodologies
Nice to Have:
- Knowledge of digital design flows and ASIC/FPGA design
- Experience with design optimization and timing convergence
If you're a motivated and experienced STA engineer looking for a new challenge, let's connect!
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