Silicon Design Engineer - Onsite

Title: Silicon Design Engineer - Onsite

Description:

SENIOR SILICON DESIGN ENGINEER

THE ROLE:
This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification

THE PERSON:
Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams

RESPONSIBILTIES:
This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

PREFERRED SKILLED SETS:
Major in EE, CS or related, master s degree with 3+ years or Bachelor with 5+ years working experience, preferably with high speed multi-gigabit SerDes PHY designs or other high performance IP designs
Proficiency in Python and/or Perl is required. Additional languages are a plus.
Versatility with scripts to automate design flow, and quality checks.
Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation

EDUCATION:
Major in EE, CS or related, master s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.

Mandatory skills:

automate design flow, quality checks,
automated synthesis, RTL blocks, Verilog, high speed Datapath, control logic applications, GDS,
automated design flows, clock tree synthesis, clock gating techniques, power gating techniques, buffer insertion, repeater insertion, scan stitching, design optimization, design cycle time reduction,
digital circuit techniques, robust implementation topologies, logic functions, logic optimization, circuit topologies, high speed, low power applications,
floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical quality, timing quality, electrical quality, IP delivery

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :

Account co-ordinator: Godwin D Antony Raj

VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008
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