Overview
On Site
$51 - $58
Contract - W2
Contract - 12 month(s)
No Travel Required
Skills
IP Design Engineer
Job Details
Job Description:
Pay Range: $51.72hr - $58.62hr
- Soft IP Development for client FPGA's using Verilog/Systemverilog.
- IntegXX third party IP cores into an FPGA system, create custom RTL wrappers for third party cores, and interface with IP vendors.
- Work with Verification Engineers to verify IP and debug issues.
- Participate in board bring up as well as system level integration.
- 7 to 12 years of experience in digital design.
- RTL coding experience using Verilog and/or System Verilog.
- Strong in digital design, micro architecture , RTL development.
- Working experience of client/Xilinx FPGA and Vivado.
- Experience in Video domain (DisplayPort/MIPI/HDMI/SDI) is preferred.
- Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces IPs/Solutions.
- Good understanding of system design aspects and its impact on performance and throughput.
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