FPGA/IP Design Engineer

Overview

Remote
$50 - $60
Contract - W2
Contract - Independent
Contract - 12 Month(s)

Skills

FPGA
RTL
Verilog

Job Details

IP Design Engineer

Position is 100% remote
Interview process is with MS Teams
Contract role

JOB DUTIES:

1. Soft IP Development for FPGA's using Verilog/Systemverilog.
2. Integrate third party IP cores into an FPGA system, create custom RTL wrappers for third party cores, and interface with IP vendors
2. Work with Verification Engineers to verify IP and debug issues.
3. Participate in board bring up as well as system level integration.
EXPERIENCE AND EDUCATION:

7 to 12 years of experience in digital design
RTL coding experience using Verilog and/or System Verilog
Strong in digital design, micro architecture , RTL development
Working experience of AMD/Xilinx FPGA and Vivado
Experience in Video domain (DisplayPort/MIPI/HDMI/SDI) is preferred
Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces IPs/Solutions
Good understanding of system design aspects and its impact on performance and throughput

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