Design Verification Engineer (GPU)

Design Verification Engineer (GPU)

- Local to market in San Jose

- Hybrid onsite 3 days per week

Role and Responsibilities:

• Work with architects and designers to build verification environments and test plans
• Analyze failing tests to root cause along, working with RTL and reference modeling teams
• Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
• Examine code coverage results, identifying exclusions and improving stimulus

Minimum requirements:

- Knowledge of Block-level (unit level)

- Debugging and development

- UVM, SystemVerilog exp

- 8 to 10 years of hands-on related exp

• BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
• Proficient in System Verilog/UVM/OVM, and OOP/C++
• Deep understanding of constrained randomization and the development of efficient test suites
• Experience with code coverage and functional coverage-driven verification methodology.
• Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.
• Working knowledge of scripting languages such as Python or Perl
• Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines Preferred qualifications:
• MS CE/EE with 5+ years of industry experience in verification
• Experience of GPU or is a plus