Overview
On Site
Full Time
Part Time
Accepts corp to corp applications
Contract - Independent
Contract - W2
Skills
SystemVerilog
UVM
EDA
Data Analysis
Synopsys
Cadence
Scripting
Python
Tcl
Perl
Emulation
ASIC
GPU
CPU
Interfaces
PCI Express
DDR SDRAM
Job Details
Role: Senior SOC/ASIC Verification Engineer
Location: Arizona - Onsite
Contract
We're seeking an experienced Design Verification Engineer with 8 10 years of hands-on expertise in SystemVerilog/UVM, EDA tools (Synopsys/Cadence), and scripting (Python, TCL, Perl). Must have experience in functional verification, assertions, and emulation, with a strong track record in ASIC development. Background in verifying GPU/CPU, high-speed interfaces (PCIe, DDR), or data center applications is a plus.
Location: Arizona - Onsite
Contract
We're seeking an experienced Design Verification Engineer with 8 10 years of hands-on expertise in SystemVerilog/UVM, EDA tools (Synopsys/Cadence), and scripting (Python, TCL, Perl). Must have experience in functional verification, assertions, and emulation, with a strong track record in ASIC development. Background in verifying GPU/CPU, high-speed interfaces (PCIe, DDR), or data center applications is a plus.
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