Overview
On Site
Depends on Experience
Contract - Independent
Contract - W2
Skills
ASIC
Cadence
Change Data Capture
Computer Engineering
DFT
Digital Design
Documentation
Electrical Engineering
Formal Verification
IP
Integrated Circuit
Intellectual Property
LEC
Mentorship
Perl
Physical Data Model
Python
RTL
Scripting
SpyGlass
Static Timing Analysis
Synopsys
SystemVerilog
TCM
Tcl
Verilog
Job Details
Job Role: Hardware Engineer Mid
Location: San Jose, CA (5 Days Onsite)
Duration: 12 months, possible extension
Job Description:
Technical:
- Being a member of design team who oversees full chip STA and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
- Option to also do block level RTL design or block or top-level IP integration.
- Helping develops efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
- Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
- Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
- Creating fullchip clocking diagrams and related documentation.
What we are looking for:
Minimum Qualifications
- Bachelor s degree in electrical or computer engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
- Experience with block/full chip STA /SDC development in functional and test modes.
- Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
- Understanding of related digital design concepts (eg. clocking and async boundaries)
- Experience with synthesis tools (eg. Synopsys ), Verilog/System Verilog programming
Preferred Qualifications
- Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) Experience with Spyglass CDC and glitch analysis Experience using Formal Verification: Synopsys Formality and Cadence LEC.
- Experience with scripting languages such as Python, Perl, or TCL
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.