IC Layout Engineer

What You ll Be Doing:

• Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
• Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
• Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
• Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
• Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
• Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
• Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

The Impact You Will Have:

• Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
• Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.
• Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
• Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
• Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
• Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

What You ll Need:

• MSc in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.
• 8+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
• Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
• Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.
• Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
• Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
• Experience with Synopsys EDA tools is highly desirable.