Overview
On Site
Full Time
Part Time
Accepts corp to corp applications
Contract - Independent
Contract - W2
Skills
PASS
Conflict Resolution
Problem Solving
Debugging
SystemVerilog
C
Scripting
Art
Testing
RTL
Mixed-signal Integrated Circuit
Test Plans
Reporting
Communication
UVM
DPI
Database
Job Details
Title: SOC Design Verification Engineer
Location: Santa Clara, CA
Duration: 6+ Months
Location: Santa Clara, CA
Duration: 6+ Months
Job Description:
Basic Qualifications:
Bachelor's degree in electrical / communications engineering or computer science
3 to 5+ years of experience in verification preferably in communication systems
Proven track record where products have gone to volume production, preferably 1st pass Silicon.
Strong written and verbal skills
Strong problem solving and debugging skills
Strong proficiency in SystemVerilog, UVM, C, System C and good scripting skills.
Key Responsibilities:
Role/Responsibilities
Implement a state-of-the-art verification environment to facilitate testing of the RTL against reference analog/Mixed-signal design models
Develop detailed test plans and write tests, run regressions, collect coverage matrices, and report progress to the program.
Work with the design and Communication systems team and participate in System level verification using test benches constructed using UVM, System C and DPI-C.
Develop a highly automated environment to run regressions that can be used to make builds and maintain the sanity of the database.
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